As is well known in the art of semiconductor fabrication, following singulation of die from a semiconductor wafer, the die are generally packaged, and the packaged die are in turn mounted to a circuit board. While packaging semiconductor die is commonplace to execute bonding between the die and the circuit board, one new method, direct chip attach (DCA) eliminates the conventional package, in favor of directly bonding the chip to the circuit board. In both conventional packages and DCA, one method of bonding the semiconductor die to a substrate or to a circuit board calls for forming a plurality of solder bumps along a main surface of the die, flipping the die over, and reflowing the solder bumps while in contact with the substrate or circuit board. Such a process is known as a "flip-chip" bonding technique.
Solder bumps for flip-chip bonding may be formed by any one of various methods, the so called "C4" (controlled collapse chip connection) process, and E3 (extended evaporated eutectic) process. In each of these processes, bumps are made by evaporating a combination of lead and tin through a screen, and onto under bump metallization (UBM) that overlies bond pads. While the C4 and E3 processes are effective to form quality solder bumps on a semiconductor die, each is relatively expensive and sophisticated.
In an effort to simplify the bump forming process and decrease cost, electroless and electrolytic plating processes have been developed. In electroless and electrolytic plating, the bumps are generally formed of a lower melting point eutectic solder, 63% Sn, 37% Pb. In contrast, the C4 process generally forms solder comprising 97% Pb, 3% Sn.
Turning to the drawings, FIG. 1 illustrates a basic cross-section of a solder bump structure formed by the known electroplating process. While a single solder bump structure is shown in FIG. 1, it is understood that an array of solder bump structures is generally formed along a surface of the substrate. As shown, an aluminum pad 102 is formed on silicon die 100. Subsequently, a passivation layer 104 is blanket deposited over the silicon substrate and pads 102. Selective etching is carried out to expose the pads 102, and under bump metallization (UBM) layer 106 is blanket deposited and patterned. Generally, the passivation layer 104 is formed of glassy silicon dioxide, and the UBM layer is formed by sputtering titanium, tungsten and copper. Subsequently, copper stud 108 is electroplated so as to selectively overlie the UBM layer 106. The components of the solder bump structure are completed by electroplating lead and tin to form solder bump 110 that overlies the copper stud 108. Here, a copper stud 108 provides an interface for nucleation and growth of tin. The solder bump 110 is then reflowed, so as to assume the generally spherical shape shown in FIG. 1.
The above-described process for forming a solder bump is generally known in the art and is generally effective for providing a bump for bonding the silicon die 100 to a substrate or to a printed circuit board via DCA. However, it has been understood by the present inventors that cracks tend to form in the passivation layer 104, during actual use of a device incorporating the silicon die 100. More particularly, it has been discovered that cracks tend to form in critical area A depicted in FIG. 1. Such cracks tend to propagate unimpeded along the die passivation layer, which may lead to failure of the circuitry in silicon die 100. In this regard, it has been recognized by the present inventors that the cracks will at times form in critical area A is due to stresses, both thermal and mechanical, during actual use of the semiconductor die in an electronic device. For example, thermal expansion coefficient mismatch between the circuit board and the silicon substrate causes thermal stress cracks in passivation layer 104, in critical area A. Accordingly, a need exists in the art for an improved solder bump structure that is more robust, and resistant to cracking due to thermal stresses and mechanical stresses.